OpenSSD Cosmos+ Platform Firmware  0.0.2
The firmware of Cosmos+ OpenSSD Platform for TOSHIBA nand flash module.
main.c
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1
2// main.c for Cosmos+ OpenSSD
3// Copyright (c) 2016 Hanyang University ENC Lab.
4// Contributed by Yong Ho Song <yhsong@enc.hanyang.ac.kr>
5// Youngjin Jo <yjjo@enc.hanyang.ac.kr>
6// Sangjin Lee <sjlee@enc.hanyang.ac.kr>
7// Jaewook Kwak <jwkwak@enc.hanyang.ac.kr>
8// Kibin Park <kbpark@enc.hanyang.ac.kr>
9//
10// This file is part of Cosmos+ OpenSSD.
11//
12// Cosmos+ OpenSSD is free software; you can redistribute it and/or modify
13// it under the terms of the GNU General Public License as published by
14// the Free Software Foundation; either version 3, or (at your option)
15// any later version.
16//
17// Cosmos+ OpenSSD is distributed in the hope that it will be useful,
18// but WITHOUT ANY WARRANTY; without even the implied warranty of
19// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
20// See the GNU General Public License for more details.
21//
22// You should have received a copy of the GNU General Public License
23// along with Cosmos+ OpenSSD; see the file COPYING.
24// If not, see <http://www.gnu.org/licenses/>.
26
28// Company: ENC Lab. <http://enc.hanyang.ac.kr>
29// Engineer: Sangjin Lee <sjlee@enc.hanyang.ac.kr>
30// Jaewook Kwak <jwkwak@enc.hanyang.ac.kr>
31// Kibin Park <kbpark@enc.hanyang.ac.kr>
32//
33// Project Name: Cosmos+ OpenSSD
34// Design Name: Cosmos+ Firmware
35// Module Name: Main
36// File Name: main.c
37//
38// Version: v1.0.2
39//
40// Description:
41// - initializes caches, MMU, exception handler
42// - calls nvme_main function
44
46// Revision History:
47//
48// * v1.0.2
49// - An address region (0x0020_0000 ~ 0x179F_FFFF) is used to uncached & nonbuffered region
50// - An address region (0x1800_0000 ~ 0x3FFF_FFFF) is used to cached & buffered region
51//
52// * v1.0.1
53// - Paging table setting is modified for QSPI or SD card boot mode
54// * An address region (0x0010_0000 ~ 0x001F_FFFF) is used to place code, data, heap and stack sections
55// * An address region (0x0010_0000 ~ 0x001F_FFFF) is setted a cached&bufferd region
56//
57// * v1.0.0
58// - First draft
60
61#include "xil_cache.h"
62#include "xil_exception.h"
63#include "xil_mmu.h"
64#include "xparameters_ps.h"
65#include "xscugic_hw.h"
66#include "xscugic.h"
67#include "xil_printf.h"
68#include "debug.h"
69
70#include "nvme/nvme.h"
71#include "nvme/nvme_main.h"
72#include "nvme/host_lld.h"
73
75
76int main()
77{
78 unsigned int u;
79
80 XScuGic_Config *IntcConfig;
81
85
86// Paging table set
87#define MB (1024 * 1024)
88 for (u = 0; u < 4096; u++)
89 {
90 if (u < 0x2)
91 Xil_SetTlbAttributes(u * MB, 0xC1E); // cached & buffered
92 else if (u < 0x180)
93 Xil_SetTlbAttributes(u * MB, 0xC12); // uncached & nonbuffered
94 else if (u < 0x400)
95 Xil_SetTlbAttributes(u * MB, 0xC1E); // cached & buffered
96 else
97 Xil_SetTlbAttributes(u * MB, 0xC12); // uncached & nonbuffered
98 }
99
103 xil_printf("[!] MMU has been enabled.\r\n");
104
105 xil_printf("\r\n Hello COSMOS+ OpenSSD !!! \r\n");
106
108
110 XScuGic_CfgInitialize(&GicInstance, IntcConfig, IntcConfig->CpuBaseAddress);
112 &GicInstance);
113
115
117
118 // Enable interrupts in the Processor.
121
122 dev_irq_init();
123
124 nvme_main();
125
126 xil_printf("done\r\n");
127
128 return 0;
129}
#define Xil_DisableMMU(...)
Definition: bsp.h:43
#define XPAR_SCUGIC_SINGLE_DEVICE_ID
Definition: bsp.h:53
#define Xil_EnableMMU(...)
Definition: bsp.h:42
#define XIL_EXCEPTION_IRQ
Definition: bsp.h:35
#define Xil_ExceptionInit(...)
Definition: bsp.h:44
#define Xil_ICacheEnable(...)
Definition: bsp.h:38
#define Xil_SetTlbAttributes(...)
Definition: bsp.h:48
#define Xil_ICacheDisable(...)
Definition: bsp.h:39
#define Xil_ExceptionEnable(...)
Definition: bsp.h:45
#define Xil_ExceptionEnableMask(...)
Definition: bsp.h:46
#define XIL_EXCEPTION_ID_INT
Definition: bsp.h:36
#define Xil_DCacheDisable(...)
Definition: bsp.h:41
#define XScuGic_LookupConfig(...)
Definition: bsp.h:51
#define XScuGic_Enable(...)
Definition: bsp.h:49
#define Xil_DCacheEnable(...)
Definition: bsp.h:40
#define XScuGic_Connect(...)
Definition: bsp.h:50
#define Xil_ExceptionRegisterHandler(...)
Definition: bsp.h:47
#define XScuGic_CfgInitialize(...)
Definition: bsp.h:52
void dev_irq_init()
Definition: host_lld.c:66
void dev_irq_handler()
Definition: host_lld.c:86
#define MB
XScuGic GicInstance
Definition: main.c:74
int main()
Definition: main.c:76
void nvme_main()
Definition: nvme_main.c:73
Definition: bsp.h:7
void * CpuBaseAddress
Definition: bsp.h:8