nvme_main.c File Reference

#include "xil_printf.h"
#include "debug.h"
#include "io_access.h"
#include "nvme.h"
#include "host_lld.h"
#include "nvme_main.h"
#include "nvme_admin_cmd.h"
#include "nvme_io_cmd.h"
#include "../memory_map.h"

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Functions
void	nvme_main ()

Variables
volatile NVME_CONTEXT	g_nvmeTask

Function Documentation

nvme_main()

void nvme_main

(

)

The main loop of Cosmos+ firmware.

This loop can be separated into several small parts:

• NVMe Manager

• Low-level Scheduler

  Interpret NVMe commands received from host.

  In this step, we need to check which type of the NVMe command you got:

• If it's Admin command:

    Handle it in NVMe Manager without forwarding to FTL.
  

• If it's I/O (NVM) command:

    Forward to the NVM Command Manager (FTL).
  

Do scheduling.

We need to execute the requests that were put on corresponding queue in prev part.

As described in the paper, Host DMA operations have the highest priority, so we should call the CheckDoneNvmeDmaReq first, then SchedulingNandReq.

Definition at line 73 of file nvme_main.c.

{
    unsigned int exeLlr;
    unsigned int rstCnt = 0;
 
    xil_printf("!!! Wait until FTL reset complete !!! \r\n");
 
    InitFTL();
 
    xil_printf("\r\nFTL reset complete!!! \r\n");
    xil_printf("Turn on the host PC \r\n");
 
    while (1)
    {
        exeLlr = 1;
 
        if (g_nvmeTask.status == NVME_TASK_WAIT_CC_EN)
        {
            unsigned int ccEn;
            ccEn = check_nvme_cc_en();
            if (ccEn == 1)
            {
                set_nvme_admin_queue(1, 1, 1);
                set_nvme_csts_rdy(1);
                g_nvmeTask.status = NVME_TASK_RUNNING;
                xil_printf("\r\nNVMe ready!!!\r\n");
            }
        }
        else if (g_nvmeTask.status == NVME_TASK_RUNNING)
        {
            NVME_COMMAND nvmeCmd;
            unsigned int cmdValid;
 
            cmdValid = get_nvme_cmd(&nvmeCmd.qID, &nvmeCmd.cmdSlotTag, &nvmeCmd.cmdSeqNum, nvmeCmd.cmdDword);
 
            if (cmdValid == 1)
            {
                rstCnt = 0;
                if (nvmeCmd.qID == 0)
                {
                    handle_nvme_admin_cmd(&nvmeCmd);
                }
                else
                {
                    handle_nvme_io_cmd(&nvmeCmd);
                    ReqTransSliceToLowLevel();
                    exeLlr = 0;
                }
            }
        }
        else if (g_nvmeTask.status == NVME_TASK_SHUTDOWN)
        {
            NVME_STATUS_REG nvmeReg;
            nvmeReg.dword = IO_READ32(NVME_STATUS_REG_ADDR);
            if (nvmeReg.ccShn != 0)
            {
                unsigned int qID;
                set_nvme_csts_shst(1);
 
                for (qID = 0; qID < 8; qID++)
                {
                    set_io_cq(qID, 0, 0, 0, 0, 0, 0);
                    set_io_sq(qID, 0, 0, 0, 0, 0);
                }
 
                set_nvme_admin_queue(0, 0, 0);
                g_nvmeTask.cacheEn = 0;
                set_nvme_csts_shst(2);
                g_nvmeTask.status = NVME_TASK_WAIT_RESET;
 
                // flush grown bad block info
                UpdateBadBlockTableForGrownBadBlock(RESERVED_DATA_BUFFER_BASE_ADDR);
 
                xil_printf("\r\nNVMe shutdown!!!\r\n");
            }
        }
        else if (g_nvmeTask.status == NVME_TASK_WAIT_RESET)
        {
            unsigned int ccEn;
            ccEn = check_nvme_cc_en();
            if (ccEn == 0)
            {
                g_nvmeTask.cacheEn = 0;
                set_nvme_csts_shst(0);
                set_nvme_csts_rdy(0);
                g_nvmeTask.status = NVME_TASK_IDLE;
                xil_printf("\r\nNVMe disable!!!\r\n");
            }
        }
        else if (g_nvmeTask.status == NVME_TASK_RESET)
        {
            unsigned int qID;
            for (qID = 0; qID < 8; qID++)
            {
                set_io_cq(qID, 0, 0, 0, 0, 0, 0);
                set_io_sq(qID, 0, 0, 0, 0, 0);
            }
 
            if (rstCnt >= 5)
            {
                pcie_async_reset(rstCnt);
                rstCnt = 0;
                xil_printf("\r\nPcie iink disable!!!\r\n");
                xil_printf("Wait few minute or reconnect the PCIe cable\r\n");
            }
            else
                rstCnt++;
 
            g_nvmeTask.cacheEn = 0;
            set_nvme_admin_queue(0, 0, 0);
            set_nvme_csts_shst(0);
            set_nvme_csts_rdy(0);
            g_nvmeTask.status = NVME_TASK_IDLE;
 
            xil_printf("\r\nNVMe reset!!!\r\n");
        }
 
        if (exeLlr && ((nvmeDmaReqQ.headReq != REQ_SLOT_TAG_NONE) || notCompletedNandReqCnt || blockedReqCnt))
        {
            CheckDoneNvmeDmaReq();
            SchedulingNandReq();
        }
    }
}

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Variable Documentation

g_nvmeTask

volatile NVME_CONTEXT g_nvmeTask

Definition at line 71 of file nvme_main.c.