nvme_admin_cmd.h File Reference

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Functions
unsigned int	get_num_of_queue (unsigned int dword11)
void	handle_set_features (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_get_features (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_create_io_cq (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_delete_io_cq (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_create_io_sq (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_delete_io_sq (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_identify (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_get_log_page (NVME_ADMIN_COMMAND *nvmeAdminCmd, NVME_COMPLETION *nvmeCPL)
void	handle_nvme_admin_cmd (NVME_COMMAND *nvmeCmd)

Function Documentation

get_num_of_queue()

unsigned int get_num_of_queue

(

unsigned int

dword11

)

Definition at line 59 of file nvme_admin_cmd.c.

{
    ADMIN_SET_FEATURES_NUMBER_OF_QUEUES_DW11 requested;
    ADMIN_SET_FEATURES_NUMBER_OF_QUEUES_COMPLETE allocated;
 
    requested.dword = dword11;
    xil_printf("Number of IO Submission Queues Requested (NSQR, zero-based): 0x%04X\r\n", requested.NSQR);
    xil_printf("Number of IO Completion Queues Requested (NCQR, zero-based): 0x%04X\r\n", requested.NCQR);
 
    // IO submission queue allocating
    if (requested.NSQR >= MAX_NUM_OF_IO_SQ)
        g_nvmeTask.numOfIOSubmissionQueuesAllocated = MAX_NUM_OF_IO_SQ;
    else
        g_nvmeTask.numOfIOSubmissionQueuesAllocated = requested.NSQR + 1; // zero-based -> non zero-based
 
    allocated.NSQA = g_nvmeTask.numOfIOSubmissionQueuesAllocated - 1; // non zero-based -> zero-based
 
    // IO completion queue allocating
    if (requested.NCQR >= MAX_NUM_OF_IO_CQ)
        g_nvmeTask.numOfIOCompletionQueuesAllocated = MAX_NUM_OF_IO_CQ;
    else
        g_nvmeTask.numOfIOCompletionQueuesAllocated = requested.NCQR + 1; // zero-based -> non zero-based
 
    allocated.NCQA = g_nvmeTask.numOfIOCompletionQueuesAllocated - 1; // non zero-based -> zero-based
 
    xil_printf("Number of IO Submission Queues Allocated (NSQA, zero-based): 0x%04X\r\n", allocated.NSQA);
    xil_printf("Number of IO Completion Queues Allocated (NCQA, zero-based): 0x%04X\r\n", allocated.NCQA);
 
    return allocated.dword;
}

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handle_create_io_cq()

void handle_create_io_cq	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 274 of file nvme_admin_cmd.c.

{
    ADMIN_CREATE_IO_CQ_DW10 cqInfo10;
    ADMIN_CREATE_IO_CQ_DW11 cqInfo11;
    NVME_IO_CQ_STATUS *ioCqStatus;
    unsigned int ioCqIdx;
 
    cqInfo10.dword = nvmeAdminCmd->dword10;
    cqInfo11.dword = nvmeAdminCmd->dword11;
 
    xil_printf("create cq: 0x%08X, 0x%08X\r\n", cqInfo11.dword, cqInfo10.dword);
 
    ASSERT(((nvmeAdminCmd->PRP1[0] & 0x3) == 0) && (nvmeAdminCmd->PRP1[1] < 0x10000));
    ASSERT(cqInfo11.IV < 8 && cqInfo10.QSIZE < 0x100 && 0 < cqInfo10.QID && cqInfo10.QID <= 8);
 
    ioCqIdx    = cqInfo10.QID - 1;
    ioCqStatus = g_nvmeTask.ioCqInfo + ioCqIdx;
 
    ioCqStatus->valid         = 1;
    ioCqStatus->qSzie         = cqInfo10.QSIZE;
    ioCqStatus->irqEn         = cqInfo11.IEN;
    ioCqStatus->irqVector     = cqInfo11.IV;
    ioCqStatus->pcieBaseAddrL = nvmeAdminCmd->PRP1[0];
    ioCqStatus->pcieBaseAddrH = nvmeAdminCmd->PRP1[1];
 
    set_io_cq(ioCqIdx, ioCqStatus->valid, ioCqStatus->irqEn, ioCqStatus->irqVector, ioCqStatus->qSzie,
              ioCqStatus->pcieBaseAddrL, ioCqStatus->pcieBaseAddrH);
 
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x0;
}

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handle_create_io_sq()

void handle_create_io_sq	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 213 of file nvme_admin_cmd.c.

{
    ADMIN_CREATE_IO_SQ_DW10 sqInfo10;
    ADMIN_CREATE_IO_SQ_DW11 sqInfo11;
    NVME_IO_SQ_STATUS *ioSqStatus;
    unsigned int ioSqIdx;
 
    sqInfo10.dword = nvmeAdminCmd->dword10;
    sqInfo11.dword = nvmeAdminCmd->dword11;
 
    xil_printf("create sq: 0x%08X, 0x%08X\r\n", sqInfo11.dword, sqInfo10.dword);
    /*xil_printf("QID : 0x%08X, QSIZE : 0x%08X\r\n", sqInfo10.QID, sqInfo10.QSIZE);
    xil_printf("PC : 0x%08X, QPRIO : 0x%08X, CQID : 0x%08X\r\n", sqInfo11.PC, sqInfo11.QPRIO,sqInfo11.CQID);
    xil_printf("pcieBaseAddrL : 0x%08X, pcieBaseAddrH : 0x%08X\r\n", ioSqStatus->pcieBaseAddrL,
    ioSqStatus->pcieBaseAddrH);*/
 
    ASSERT((nvmeAdminCmd->PRP1[0] & 0x3) == 0 && nvmeAdminCmd->PRP1[1] < 0x10000);
    ASSERT(0 < sqInfo10.QID && sqInfo10.QID <= 8 && sqInfo10.QSIZE < 0x100 && 0 < sqInfo11.CQID &&
           sqInfo11.CQID <= 8);
 
    ioSqIdx    = sqInfo10.QID - 1;
    ioSqStatus = g_nvmeTask.ioSqInfo + ioSqIdx;
 
    ioSqStatus->valid         = 1;
    ioSqStatus->qSzie         = sqInfo10.QSIZE;
    ioSqStatus->cqVector      = sqInfo11.CQID;
    ioSqStatus->pcieBaseAddrL = nvmeAdminCmd->PRP1[0];
    ioSqStatus->pcieBaseAddrH = nvmeAdminCmd->PRP1[1];
 
    set_io_sq(ioSqIdx, ioSqStatus->valid, ioSqStatus->cqVector, ioSqStatus->qSzie, ioSqStatus->pcieBaseAddrL,
              ioSqStatus->pcieBaseAddrH);
 
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x0;
}

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handle_delete_io_cq()

void handle_delete_io_cq	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 306 of file nvme_admin_cmd.c.

{
    ADMIN_DELETE_IO_CQ_DW10 cqInfo10;
    NVME_IO_CQ_STATUS *ioCqStatus;
    unsigned int ioCqIdx;
 
    cqInfo10.dword = nvmeAdminCmd->dword10;
 
    xil_printf("delete cq: 0x%08X\r\n", cqInfo10.dword);
 
    ioCqIdx    = (unsigned int)cqInfo10.QID - 1;
    ioCqStatus = g_nvmeTask.ioCqInfo + ioCqIdx;
 
    ioCqStatus->valid         = 0;
    ioCqStatus->irqVector     = 0;
    ioCqStatus->qSzie         = 0;
    ioCqStatus->pcieBaseAddrL = 0;
    ioCqStatus->pcieBaseAddrH = 0;
 
    set_io_cq(ioCqIdx, 0, 0, 0, 0, 0, 0);
 
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x0;
}

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handle_delete_io_sq()

void handle_delete_io_sq	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 249 of file nvme_admin_cmd.c.

{
    ADMIN_DELETE_IO_SQ_DW10 sqInfo10;
    NVME_IO_SQ_STATUS *ioSqStatus;
    unsigned int ioSqIdx;
 
    sqInfo10.dword = nvmeAdminCmd->dword10;
 
    xil_printf("delete sq: 0x%08X\r\n", sqInfo10.dword);
 
    ioSqIdx    = (unsigned int)sqInfo10.QID - 1;
    ioSqStatus = g_nvmeTask.ioSqInfo + ioSqIdx;
 
    ioSqStatus->valid         = 0;
    ioSqStatus->cqVector      = 0;
    ioSqStatus->qSzie         = 0;
    ioSqStatus->pcieBaseAddrL = 0;
    ioSqStatus->pcieBaseAddrH = 0;
 
    set_io_sq(ioSqIdx, 0, 0, 0, 0, 0);
 
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x0;
}

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handle_get_features()

void handle_get_features	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 152 of file nvme_admin_cmd.c.

{
    ADMIN_GET_FEATURES_DW10 features;
    NVME_COMPLETION cpl;
 
    features.dword = nvmeAdminCmd->dword10;
 
    switch (features.FID)
    {
    case LBA_RANGE_TYPE:
    {
        ASSERT(nvmeAdminCmd->NSID == 1);
 
        cpl.dword[0]       = 0x0;
        cpl.statusField.SC = SC_INVALID_FIELD_IN_COMMAND;
        nvmeCPL->dword[0]  = cpl.dword[0];
        nvmeCPL->specific  = 0x0;
        break;
    }
    case TEMPERATURE_THRESHOLD:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = nvmeAdminCmd->dword11;
        break;
    }
    case VOLATILE_WRITE_CACHE:
    {
 
        xil_printf("Get VWC: %X\r\n", g_nvmeTask.cacheEn);
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = g_nvmeTask.cacheEn;
        break;
    }
    case POWER_MANAGEMENT:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case Power_State_Transition:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case 0xD0:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    default:
    {
        xil_printf("Not Support FID (Get): %X\r\n", features.FID);
        ASSERT(0);
        break;
    }
    }
    xil_printf("Get Feature FID:%X\r\n", features.FID);
}

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handle_get_log_page()

void handle_get_log_page	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 384 of file nvme_admin_cmd.c.

{
    // ADMIN_GET_LOG_PAGE_DW10 getLogPageInfo;
 
    // unsigned int prp1[2];
    // unsigned int prp2[2];
    // unsigned int prpLen;
 
    // getLogPageInfo.dword = nvmeAdminCmd->dword10;
 
    // prp1[0] = nvmeAdminCmd->PRP1[0];
    // prp1[1] = nvmeAdminCmd->PRP1[1];
    // prpLen = 0x1000 - (prp1[0] & 0xFFF);
 
    // prp2[0] = nvmeAdminCmd->PRP2[0];
    // prp2[1] = nvmeAdminCmd->PRP2[1];
 
    // xil_printf("ADMIN GET LOG PAGE\n");
 
    // LID
    // Mandatory//1-Error information, 2-SMART/Health information, 3-Firmware Slot information
    // Optional//4-ChangedNamespaceList, 5-Command Effects Log
    // xil_printf("LID: 0x%X, NUMD: 0x%X \r\n", getLogPageInfo.LID, getLogPageInfo.NUMD);
 
    // xil_printf("PRP1[63:32] = 0x%X, PRP1[31:0] = 0x%X", prp1[1], prp1[0]);
    // xil_printf("PRP2[63:32] = 0x%X, PRP2[31:0] = 0x%X", prp2[1], prp2[0]);
 
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x9; // invalid log page
}

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handle_identify()

void handle_identify	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 331 of file nvme_admin_cmd.c.

{
    ADMIN_IDENTIFY_COMMAND_DW10 identifyInfo;
    unsigned int pIdentifyData = ADMIN_CMD_DRAM_DATA_BUFFER;
    unsigned int prp[2];
    unsigned int prpLen;
 
    identifyInfo.dword = nvmeAdminCmd->dword10;
 
    if (identifyInfo.CNS == 1)
    {
        if ((nvmeAdminCmd->PRP1[0] & 0x3) != 0 || (nvmeAdminCmd->PRP2[0] & 0x3) != 0)
            xil_printf("CI: %X, %X, %X, %X\r\n", nvmeAdminCmd->PRP1[1], nvmeAdminCmd->PRP1[0],
                       nvmeAdminCmd->PRP2[1], nvmeAdminCmd->PRP2[0]);
 
        ASSERT((nvmeAdminCmd->PRP1[0] & 0x3) == 0 && (nvmeAdminCmd->PRP2[0] & 0x3) == 0);
        identify_controller(pIdentifyData);
    }
    else if (identifyInfo.CNS == 0)
    {
        if ((nvmeAdminCmd->PRP1[0] & 0x3) != 0 || (nvmeAdminCmd->PRP2[0] & 0x3) != 0)
            xil_printf("NI: %X, %X, %X, %X\r\n", nvmeAdminCmd->PRP1[1], nvmeAdminCmd->PRP1[0],
                       nvmeAdminCmd->PRP2[1], nvmeAdminCmd->PRP2[0]);
        // ASSERT(nvmeAdminCmd->NSID == 1);
        ASSERT((nvmeAdminCmd->PRP1[0] & 0x3) == 0 && (nvmeAdminCmd->PRP2[0] & 0x3) == 0);
        identify_namespace(pIdentifyData);
    }
    else
        ASSERT(0);
 
    prp[0] = nvmeAdminCmd->PRP1[0];
    prp[1] = nvmeAdminCmd->PRP1[1];
 
    prpLen = 0x1000 - (prp[0] & 0xFFF);
    //  xil_printf("prpLen = %X, prp[1] = %X, prp[0] = %X\r\n",prpLen, prp[1], prp[0]);
    set_direct_tx_dma(pIdentifyData, prp[1], prp[0], prpLen);
    if (prpLen != 0x1000)
    {
        pIdentifyData = pIdentifyData + prpLen;
        prpLen        = 0x1000 - prpLen;
        prp[0]        = nvmeAdminCmd->PRP2[0];
        prp[1]        = nvmeAdminCmd->PRP2[1];
 
        //      ASSERT((prp[1] & 0xFFF) == 0);
        //      xil_printf("prpLen = %X, prp[1] = %X, prp[0] = %X\r\n",prpLen, prp[1], prp[0]);
        set_direct_tx_dma(pIdentifyData, prp[1], prp[0], prpLen);
    }
 
    check_direct_tx_dma_done();
    nvmeCPL->dword[0] = 0;
    nvmeCPL->specific = 0x0;
}

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handle_nvme_admin_cmd()

void handle_nvme_admin_cmd

(

NVME_COMMAND *

nvmeCmd

)

Definition at line 415 of file nvme_admin_cmd.c.

{
    NVME_ADMIN_COMMAND *nvmeAdminCmd;
    NVME_COMPLETION nvmeCPL;
    unsigned int opc;
    unsigned int needCpl;
    unsigned int needSlotRelease;
 
    nvmeAdminCmd = (NVME_ADMIN_COMMAND *)nvmeCmd->cmdDword;
    opc          = (unsigned int)nvmeAdminCmd->OPC;
 
    needCpl         = 1;
    needSlotRelease = 0;
 
    /*  xil_printf("OPC = 0x%X\r\n", nvmeAdminCmd->OPC);
                    xil_printf("FUSE = 0x%X\r\n", nvmeAdminCmd->FUSE);
                    xil_printf("PSDT = 0x%X\r\n", nvmeAdminCmd->PSDT);
                    xil_printf("CID = 0x%X\r\n",nvmeAdminCmd->CID);
                    xil_printf("NSID = 0x%X\r\n", nvmeAdminCmd->NSID);
                    xil_printf("MPTR[1] = 0x%X, MPTR[0] = 0x%X\r\n", nvmeAdminCmd->MPTR[1], nvmeAdminCmd->MPTR[0]);
                    xil_printf("PRP1[63:32] = 0x%X, PRP1[31:0] = 0x%X\r\n", nvmeAdminCmd->PRP1[1],
       nvmeAdminCmd->PRP1[0]); xil_printf("PRP2[63:32] = 0x%X, PRP2[31:0] = 0x%X\r\n", nvmeAdminCmd->PRP2[1],
       nvmeAdminCmd->PRP2[0]); xil_printf("dword10 = 0x%X\r\n", nvmeAdminCmd->dword10); xil_printf("dword11 =
       0x%X\r\n", nvmeAdminCmd->dword11); xil_printf("dword12 = 0x%X\r\n", nvmeAdminCmd->dword12);
                    xil_printf("dword13 = 0x%X\r\n", nvmeAdminCmd->dword13);
                    xil_printf("dword14 = 0x%X\r\n", nvmeAdminCmd->dword14);
                    xil_printf("dword15 = 0x%X\r\n", nvmeAdminCmd->dword15);*/
    switch (opc)
    {
    case ADMIN_SET_FEATURES:
    {
        handle_set_features(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_CREATE_IO_CQ:
    {
        handle_create_io_cq(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_CREATE_IO_SQ:
    {
        handle_create_io_sq(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_IDENTIFY:
    {
        handle_identify(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_GET_FEATURES:
    {
        handle_get_features(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_DELETE_IO_CQ:
    {
        handle_delete_io_cq(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_DELETE_IO_SQ:
    {
        handle_delete_io_sq(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_ASYNCHRONOUS_EVENT_REQUEST:
    {
        needCpl          = 0;
        needSlotRelease  = 1;
        nvmeCPL.dword[0] = 0;
        nvmeCPL.specific = 0x0;
        break;
    }
    case ADMIN_GET_LOG_PAGE:
    {
        handle_get_log_page(nvmeAdminCmd, &nvmeCPL);
        break;
    }
    case ADMIN_SECURITY_RECEIVE:
    {
        needCpl          = 0;
        needSlotRelease  = 0;
        nvmeCPL.dword[0] = 0;
        nvmeCPL.specific = 0x0;
        break;
    }
    case ADMIN_DOORBELL_BUFFER_CONFIG:
    {
        needCpl          = 0;
        needSlotRelease  = 0;
        nvmeCPL.dword[0] = 0;
        nvmeCPL.specific = 0x0;
        break;
    }
    default:
    {
        xil_printf("Not Support Admin Command OPC: %X\r\n", opc);
        ASSERT(0);
        break;
    }
    }
 
    if (needCpl == 1)
        set_auto_nvme_cpl(nvmeCmd->cmdSlotTag, nvmeCPL.specific, nvmeCPL.statusFieldWord);
    else if (needSlotRelease == 1)
        set_nvme_slot_release(nvmeCmd->cmdSlotTag);
    else
 
        set_nvme_cpl(nvmeCmd->qID, nvmeAdminCmd->CID, nvmeCPL.specific, nvmeCPL.statusFieldWord);
 
    xil_printf("Done Admin Command OPC: %X\r\n", opc);
}

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handle_set_features()

void handle_set_features	(	NVME_ADMIN_COMMAND *	nvmeAdminCmd,
		NVME_COMPLETION *	nvmeCPL
	)

Definition at line 90 of file nvme_admin_cmd.c.

{
    ADMIN_SET_FEATURES_DW10 features;
 
    features.dword = nvmeAdminCmd->dword10;
 
    switch (features.FID)
    {
    case NUMBER_OF_QUEUES:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = get_num_of_queue(nvmeAdminCmd->dword11);
        break;
    }
    case INTERRUPT_COALESCING:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case ARBITRATION:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case ASYNCHRONOUS_EVENT_CONFIGURATION:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case VOLATILE_WRITE_CACHE:
    {
        xil_printf("Set VWC: %X\r\n", nvmeAdminCmd->dword11);
        g_nvmeTask.cacheEn = (nvmeAdminCmd->dword11 & 0x1);
        nvmeCPL->dword[0]  = 0x0;
        nvmeCPL->specific  = 0x0;
        break;
    }
    case POWER_MANAGEMENT:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    case Timestamp:
    {
        nvmeCPL->dword[0] = 0x0;
        nvmeCPL->specific = 0x0;
        break;
    }
    default:
    {
        xil_printf("Not Support FID (Set): %X\r\n", features.FID);
        ASSERT(0);
        break;
    }
    }
    xil_printf("Set Feature FID:%X\r\n", features.FID);
}

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